1. Field of the Invention
The present invention is directed to aggregating functionality on a single application specific integrated circuit (ASIC). More specifically, the present invention is directed to a system for providing a plurality of modes and interconnectability between ASICs to achieve scaling.
2. Related Art
Conventional memory controller boards comprise a number of application specific integrated circuits (ASICs). The ASICs can be functionally divided into three categories: memory input, memory output, and memory controller. Memory input ASICs accept inputs from requesters. A requester requests access to memory. The memory input ASIC provides the requester with the means to input the request to memory. The memory input ASIC routes a request to a memory controller ASIC. The memory controller ASIC processes the request and determines the appropriate memory accesses required to handle the request. For example, for a READ request, the memory controller ASIC determines the address of the request, performs a memory access, and obtains the data at the requested address. The memory output ASIC in conventional systems functions to return data to the requester. In the case of the READ request above, for example, data to be returned to the requester is sent to the memory output ASIC for subsequent return to the requester.
There are several problems with the conventional design. First, a separate ASIC must be designed for each function: memory input, memory output, and memory control. This increases system design and fabrication cost. Moreover, interconnectivity between functions is not flexible. That is, the ASIC's configuration cannot be changed as system requirements change. In addition, because of the inflexible interconnectivity, designs using conventional ASICs are not scalable. That is, it is difficult to expand the capability of the system without adding new boards. Addition of new boards, significantly increases system costs.
Thus, what is desired is an ASIC design that reduces or eliminates the need for separate ASIC designs for separate functionality. In addition, the design methodology should provide flexible interconnectivity between functionality, as well as provide scalability to grow as system requirements grow.